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Disambiguation of "Wang, Yih"

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A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.

, , , , , , , and . J. Solid-State Circuits, 46 (1): 76-84 (2011)

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Dr. rer. nat. Lei Wang University of Stuttgart

Zhe Wang University of Stuttgart

Dr. Dongren Wang University of Stuttgart

Yi Wang University of Stuttgart

Yao Wang University of Stuttgart

 

Other publications of authors with the same name

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design., , , , , , and . IEEE Design & Test of Computers, 28 (1): 22-31 (2011)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 43 (1): 172-179 (2008)Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 44 (4): 1199-1208 (2009)A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology., , , , , , , , , and . J. Solid-State Circuits, 44 (1): 148-154 (2009)A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation., , , , , , , and . J. Solid-State Circuits, 46 (1): 76-84 (2011)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry., , , , , , , , and . ISSCC, page 230-232. IEEE, (2012)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology., , , , , , , , , and 2 other author(s). VLSIC, page 1-2. IEEE, (2014)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology., , , , , , , , , and . ISSCC, page 376-377. IEEE, (2008)