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A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology.

, , , , , , , , , and . J. Solid-State Circuits, 44 (1): 148-154 (2009)

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Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits., , , , and . DAC, page 489-494. ACM Press, (1998)A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS., , , , , and . J. Solid-State Circuits, 45 (4): 863-868 (2010)IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions., , , and . IEEE Design & Test of Computers, 19 (2): 24-33 (2002)On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques., , and . IEEE Trans. VLSI Syst., 9 (5): 718-725 (2001)Efficient statistical approach to estimate power considering uncertain properties of primary inputs., , and . IEEE Trans. VLSI Syst., 6 (3): 484-492 (1998)Estimation of power dissipation using a novel power macromodelingtechnique., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (11): 1363-1369 (2000)A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology., , , , , , , , , and . J. Solid-State Circuits, 44 (1): 148-154 (2009)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 43 (1): 172-179 (2008)Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs., , and . ICCAD, page 40-44. IEEE Computer Society / ACM, (1997)A Power Macromodeling Technique Based on Power Sensitivity., and . DAC, page 678-683. ACM Press, (1998)