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Disambiguation of "Somasekhar, Dinesh"

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Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.

, , , , , , , , , , , , and . J. Solid-State Circuits, 44 (4): 1199-1208 (2009)

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Dr. phil. Dinesh Vemula University of Stuttgart

 

Other publications of authors with the same name

Leakage control with efficient use of transistor stacks in single threshold CMOS., , , and . IEEE Trans. VLSI Syst., 10 (1): 1-5 (2002)System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. VLSI Syst., 24 (12): 3468-3476 (2016)LVDCSL: low voltage differential current switch logic, a robust low power DCSL family., and . ISLPED, page 18-23. ACM, (1997)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches., , , and . ISCAS, IEEE, (2006)IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits., , and . Great Lakes Symposium on VLSI, page 243-248. IEEE Computer Society, (1998)Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 105-108 (2016)A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 42 (1): 233-242 (2007)Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process., , , , , , and . J. Solid-State Circuits, 45 (4): 751-758 (2010)Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 261-264 (2016)