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Disambiguation of "Bhattacharya, Uddalak"

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A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.

, , , , , , , , and . ISSCC, page 230-232. IEEE, (2012)

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Satavisha Bhattacharya University of Stuttgart

Somnath Bhattacharya University of Stuttgart

 

Other publications of authors with the same name

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist., , , , , and . VLSIC, page 266-. IEEE, (2015)A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (1): 150-158 (2013)A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management., , , , , , , , and . J. Solid-State Circuits, 45 (1): 103-110 (2010)A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation., , , , , , , and . J. Solid-State Circuits, 46 (1): 76-84 (2011)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry., , , , , , , , and . ISSCC, page 230-232. IEEE, (2012)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design., , , , , , and . IEEE Design & Test of Computers, 28 (1): 22-31 (2011)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 43 (1): 172-179 (2008)