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Disambiguation of "Bohr, Mark"

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A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.

, , , , , , , , and . J. Solid-State Circuits, 45 (1): 103-110 (2010)

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Mark Burkhardt University of Stuttgart

Dr. Mark Hamilton University of Stuttgart

Mark Kurcsics University of Stuttgart

Dr. rer. nat. habil. Frederik Marks University of Stuttgart

Ph. D. Mark Ringenberg University of Stuttgart

 

Other publications of authors with the same name

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology., , , , , , , , , and . J. Solid-State Circuits, 44 (1): 148-154 (2009)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 43 (1): 172-179 (2008)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology., , , , , , , , , and . ISSCC, page 376-377. IEEE, (2008)A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (1): 150-158 (2013)A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management., , , , , , , , and . J. Solid-State Circuits, 45 (1): 103-110 (2010)Silicon Trends and Limits for Advanced Microprocessors.. Commun. ACM, 41 (3): 80-87 (1998)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)The new era of scaling in an SoC world.. ISSCC, page 23-28. IEEE, (2009)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry., , , , , , , , and . ISSCC, page 230-232. IEEE, (2012)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)