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Disambiguation of "Roy, Kaushik"

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Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications.

, , , , and . DAC, page 430-435. ACM Press, (1999)

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Ph. D. Sarbani Roy University of Stuttgart

Rajarshi Roy University of Stuttgart

Ranjith Mathew Roy University of Stuttgart

 

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Secure and simplified access to home appliances using Iris recognition., , and . CIB, page 22-29. IEEE, (2009)Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection., , and . IEEE Trans. VLSI Syst., 23 (1): 208-212 (2015)Robust subthreshold logic for ultra-low power operation., , and . IEEE Trans. VLSI Syst., 9 (1): 90-99 (2001)On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques., , and . IEEE Trans. VLSI Syst., 9 (5): 718-725 (2001)Efficient statistical approach to estimate power considering uncertain properties of primary inputs., , and . IEEE Trans. VLSI Syst., 6 (3): 484-492 (1998)AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture., , , and . IEEE Trans. VLSI Syst., 22 (4): 712-720 (2014)O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era., and . IEEE Trans. VLSI Syst., 10 (3): 221-229 (2002)A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET., , and . IEEE Trans. VLSI Syst., 14 (2): 183-192 (2006)Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation., , , and . IEEE Trans. VLSI Syst., 13 (11): 1213-1224 (2005)Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors., , and . IEEE Trans. VLSI Syst., 13 (1): 75-85 (2005)