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Modeling the response of Bang-Bang digital PLLs to phase error perturbations., , , , , , and . CICC, page 1-4. IEEE, (2012)Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses., , , , , , , , and . IEEE Trans. on Circuits and Systems, 55-I (7): 1904-1910 (2008)Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm., , , and . VLSI-DAT, page 1-4. IEEE, (2012)A Family of 32 nm IA Processors., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 119-130 (2011)Westmere: A family of 32nm IA processors., , , , , , and . ISSCC, page 96-97. IEEE, (2010)A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process., , , , , , and . J. Solid-State Circuits, 51 (2): 378-390 (2016)Low power analog circuit techniques in the 5th generation intel coreTM microprocessor (broadwell)., , , and . CICC, page 1-4. IEEE, (2015)A novel digital loop filter architecture for bang-bang ADPLL., , , , , , , and . SoCC, page 45-50. IEEE, (2012)Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control., , , , , , and . IEEE J. Solid State Circuits, 57 (1): 90-102 (2022)Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging., , , , , , , , , and 9 other author(s). ISSCC, page 292-604. IEEE, (2007)