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How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2013)I/O Self-Leakage Test., , , and . ITC, page 903-906. IEEE Computer Society, (2004)Re: Search., , and . New Media & Society, 15 (8): 1366-1373 (2013)On-Die Supply-Resonance Suppression Using Band-Limited Active Damping., , , , , , , , , and 1 other author(s). ISSCC, page 286-603. IEEE, (2007)Modeling the response of Bang-Bang digital PLLs to phase error perturbations., , , , , , and . CICC, page 1-4. IEEE, (2012)A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 43 (1): 61-68 (2008)A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process., , , , and . J. Solid-State Circuits, 44 (12): 3621-3630 (2009)A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation., , and . J. Solid-State Circuits, 54 (9): 2487-2500 (2019)Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor., , , , and . ISLPED, page 304-309. ACM, (2007)HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system., , , , and . CICC, page 1-4. IEEE, (2010)