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Disambiguation of "Song, Taigon"

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How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.

, , , , , , , , , , , , and . CICC, page 1-4. IEEE, (2013)

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Dr. rer. nat. Bin Song University of Stuttgart

Han Song University of Stuttgart

Qian Song University of Stuttgart

Jianing Song University of Stuttgart

Bowen Song University of Stuttgart

 

Other publications of authors with the same name

Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (12): 1900-1913 (2014)3D-MAPS: 3D Massively parallel processor with stacked memory., , , , , , , , , and 13 other author(s). ISSCC, page 188-190. IEEE, (2012)Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs., , , and . ICCAD, page 649-655. IEEE, (2015)Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)., , , , , , , , , and 13 other author(s). IEEE Trans. Computers, 64 (1): 112-125 (2015)How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2013)Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs., and . J. Inform. and Commun. Convergence Engineering, (2015)Signal integrity analysis and optimization for 3D ICs., , and . ISQED, page 42-49. IEEE, (2011)More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (12): 2056-2067 (2016)Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs., , , and . IEEE Trans. VLSI Syst., 24 (5): 1636-1648 (2016)Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs., , , and . DAC, page 180:1-180:7. ACM, (2013)