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Disambiguation of "Jung, Moongon"

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How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.

, , , , , , , , , , , , and . CICC, page 1-4. IEEE, (2013)

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Univ. -Prof. Dr. -Ing. Hans Christian Jünger University of Stuttgart

Zukunftsthemen heute gestalten : BBB-Memorandum, , , , , and . Bau aktuell, 14 (1): 28-34 (2023)

Mathias Jung University of Stuttgart

Philipp Junger

Dr. Kerstin Jung University of Stuttgart

Tobias Junginger University of Stuttgart

 

Other publications of authors with the same name

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC., , , and . Commun. ACM, 57 (1): 107-115 (2014)On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective., , , , and . DAC, page 4:1-4:6. ACM, (2014)Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs., , , and . ASP-DAC, page 687-692. IEEE, (2013)Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)., , , , , , , , , and 13 other author(s). IEEE Trans. Computers, 64 (1): 112-125 (2015)Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC., , , , and . ICCAD, page 563-570. IEEE Computer Society, (2011)TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC., , , and . DAC, page 188-193. ACM, (2011)3D-MAPS: 3D Massively parallel processor with stacked memory., , , , , , , , , and 13 other author(s). ISSCC, page 188-190. IEEE, (2012)How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2013)Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (11): 1694-1707 (2013)TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (8): 1194-1207 (2012)