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Disambiguation of "Sheikh, Farhana"

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A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.

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Other publications of authors with the same name

A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS., , , , , , , and . IEEE J. Solid State Circuits, 48 (1): 128-139 (2013)53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 767-776 (2011)2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2807-2821 (2012)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS., , , , , , , and . VLSIC, page 118-119. IEEE, (2012)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS., , , , , , and . ESSCIRC, page 177-180. IEEE, (2012)18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication., , , , , , , and . SiPS, page 1-6. IEEE, (2015)A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET., , , , and . VLSI Circuits, page 23-24. IEEE, (2018)Minimum-power retiming for dual-supply CMOS circuits., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 43-49. ACM, (2002)A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS., , , , , , and . IEEE J. Solid State Circuits, 48 (1): 118-127 (2013)