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Disambiguation of "Lu, Shih-Lien"

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A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.

, , , , , , , , , , and . J. Solid-State Circuits, 46 (1): 194-208 (2011)

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Hao Lu University of Stuttgart

Yong Lu University of Stuttgart

Jun. -Prof. Dr. rer. nat. Christina Lienstromberg University of Stuttgart

Junqi Lu University of Stuttgart

Lu Chen University of Stuttgart

 

Other publications of authors with the same name

Adaptive Cache Design to Enable Reliable Low-Voltage Operation., , , , and . IEEE Trans. Computers, 60 (1): 50-63 (2011)Trading Off Cache Capacity for Low-Voltage Operation., , , , , and . IEEE Micro, 29 (1): 96-103 (2009)Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency., , , , , , , , , and . CICC, page 1-4. IEEE, (2010)Advances of the Counterflow Pipeline Microarchitecture., , and . HPCA, page 230-236. IEEE Computer Society, (1997)Design for test and reliability in ultimate CMOS., , , , , , , , , and 4 other author(s). DATE, page 677-682. IEEE, (2012)Distributed hardware matcher framework for SoC survivability., and . DATE, page 305-310. IEEE, (2011)Trading off Cache Capacity for Reliability to Enable Low Voltage Operation., , , , , and . ISCA, page 203-214. IEEE Computer Society, (2008)Reducing cache and TLB power by exploiting memory region and privilege level semantics., , , , , , and . Journal of Systems Architecture - Embedded Systems Design, 59 (6): 279-295 (2013)Design, implementation, and verification of active cache emulator (ACE)., , and . FPGA, page 63-72. ACM, (2006)Resilient circuits - Enabling energy-efficient performance and reliability., , , , and . ICCAD, page 71-73. ACM, (2009)