Author of the publication

A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications.

, , , , , , , , , and . J. Solid-State Circuits, 46 (5): 1059-1075 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

On-Chip Spectrum Analyzer for Analog Built-In Self Test., , and . VTS, page 131-136. IEEE Computer Society, (2005)A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 48 (5): 1138-1150 (2013)A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications., , , , , , , , , and . J. Solid-State Circuits, 46 (5): 1059-1075 (2011)Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C., , , , , , , , , and . J. Solid-State Circuits, 53 (9): 2512-2531 (2018)A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2012)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2012)A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI., , , , , , , , and . CICC, page 1-4. IEEE, (2013)10+ Gb/s 90nm CMOS serial link demo in CBGA package., , , , , , , and . CICC, page 27-30. IEEE, (2004)Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications., , , , , and . IBM Journal of Research and Development, 39 (1-2): 83-92 (1995)Design and Compliance Testing of a SiGe WCDMA Receiver IC With Integrated Analog Baseband., , , , and . Proceedings of the IEEE, 93 (9): 1624-1636 (2005)