PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Jose, Anup P."

Author of the publication

copydeleteadd this publication to your clipboard
On-Chip Spectrum Analyzer for Analog Built-In Self Test.

, , and . VTS, page 131-136. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jithin Jose University of Stuttgart

Basil Jose University of Stuttgart

P. Hommel

P. Abegglen

P. Krasteva

 

Other publications of authors with the same name

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 48 (11): 2582-2594 (2013)Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication., and . J. Solid-State Circuits, 42 (6): 1415-1424 (2007)Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application., , , , and . ASYNC, page 216-226. IEEE Computer Society, (2003)A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 50 (8): 1932-1944 (2015)Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2014)On-Chip Spectrum Analyzer for Analog Built-In Self Test., , and . VTS, page 131-136. IEEE Computer Society, (2005)