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Disambiguation of "Rylov, Sergey V."

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10+ Gb/s 90nm CMOS serial link demo in CBGA package.

, , , , , , , and . CICC, page 27-30. IEEE, (2004)

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apl. Prof. Dr. Sergey Oladyshkin University of Stuttgart

Sergey Abramov University of Stuttgart

V. Vaikuntanathan

V. Zaverkin

Michael P. Voigt Universität Stuttgart

 

Other publications of authors with the same name

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 47 (4): 884-896 (2012)A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2011)An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz., , , , and . IEEE Trans. VLSI Syst., 18 (7): 1043-1056 (2010)A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS., , , , , , and . ISSCC, page 98-99. IEEE, (2009)An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz., , , , and . ASYNC, page 84-95. IEEE Computer Society, (2002)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 50 (12): 3120-3132 (2015)A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 53 (4): 1214-1226 (2018)A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology., , , , , , , , , and 6 other author(s). CICC, page 1-4. IEEE, (2014)10+ Gb/s 90nm CMOS serial link demo in CBGA package., , , , , , , and . CICC, page 27-30. IEEE, (2004)A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology., , , , , , , , , and 11 other author(s). ISSCC, page 324-326. IEEE, (2012)