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%0 Journal Article
%1 journals/jssc/LeePOAYCKRAV18
%A Lee, Wooram
%A Plouchart, Jean-Olivier
%A Ozdag, Caglar
%A Aydogan, Yigit
%A Yeck, Mark
%A Cabuk, Alper
%A Kepkep, Asim
%A Reynolds, Scott K.
%A Apaydin, Emre
%A Valdes-Garcia, Alberto
%D 2018
%J J. Solid-State Circuits
%K dblp
%N 9
%P 2512-2531
%T Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#LeePOAYCKRAV18
%V 53
@article{journals/jssc/LeePOAYCKRAV18,
added-at = {2018-09-13T00:00:00.000+0200},
author = {Lee, Wooram and Plouchart, Jean-Olivier and Ozdag, Caglar and Aydogan, Yigit and Yeck, Mark and Cabuk, Alper and Kepkep, Asim and Reynolds, Scott K. and Apaydin, Emre and Valdes-Garcia, Alberto},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/22f8fc10a562cd69f51f317611ccd48bb/dblp},
ee = {https://doi.org/10.1109/JSSC.2018.2856254},
interhash = {69dab466996df7f5a09b6d57ad4d5eee},
intrahash = {2f8fc10a562cd69f51f317611ccd48bb},
journal = {J. Solid-State Circuits},
keywords = {dblp},
number = 9,
pages = {2512-2531},
timestamp = {2019-09-27T06:09:41.000+0200},
title = {Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#LeePOAYCKRAV18},
volume = 53,
year = 2018
}
