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Design and Compliance Testing of a SiGe WCDMA Receiver IC With Integrated Analog Baseband.

, , , , and . Proceedings of the IEEE, 93 (9): 1624-1636 (2005)

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Progress toward a low-cost millimeter-wave silicon radio., , , , , , , and . CICC, page 563-570. IEEE, (2005)A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology., , , , , , , , , and 11 other author(s). ISSCC, page 324-326. IEEE, (2012)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2012)A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 47 (8): 1828-1841 (2012)Design considerations for high-data-rate chip interconnect systems.. IEEE Communications Magazine, 48 (10): 174-183 (2010)Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers., , and . CICC, page 639-642. IEEE, (2007)A direct-conversion receiver integrated circuit for WCDMA mobile systems., , , , , and . IBM Journal of Research and Development, 47 (2-3): 337-354 (2003)Developing integrated antenna subsystems for laptop computers., , , , , and . IBM Journal of Research and Development, 47 (2-3): 355-367 (2003)A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2011)A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 49 (11): 2474-2489 (2014)