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Disambiguation of "Parker, Benjamin D."

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A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.

, , , , , , , , and . CICC, page 1-4. IEEE, (2013)

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D. Marino

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D. Inkermann

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D. Roth

 

Other publications of authors with the same name

A semi-digital delay-locked loop using an analog-based finite state machine., , and . IEEE Trans. on Circuits and Systems, 51-II (11): 635-639 (2004)A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS., , , , , , , and . ISSCC, page 368-369. IEEE, (2009)The Biomolecular Interaction Network Database and related tools 2005 update., , , , , , , , , and 65 other author(s). Nucleic Acids Research, 33 (Database-Issue): 418-424 (2005)A High-Resolution Minimicroscope System for Wireless Real-Time Monitoring., , , , , , and . IEEE Trans. Biomed. Engineering, 65 (7): 1524-1531 (2018)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation., , , , , , , , , and . FPGA, page 153-162. ACM, (2012)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion., , , , , , , , , and 4 other author(s). CICC, page 1-4. IEEE, (2013)22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI., , , , , , , , , and 1 other author(s). ISSCC, page 56-57. IEEE, (2016)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)