Author of the publication

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.

, , , , and . ISQED, page 88-93. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Characterization and design for variability and reliability., , and . CICC, page 341-346. IEEE, (2008)A Scheme for On-Chip Timing Characterization., , , and . VTS, page 24-29. IEEE Computer Society, (2006)Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating., , , and . IEEE Trans. VLSI Syst., 15 (11): 1215-1224 (2007)On-Chip Delay Measurement Based Response Analysis for Timing Characterization., , , , , and . J. Electronic Testing, 26 (6): 599-619 (2010)A fast hybrid carry-lookahead/carry-select adder design., , and . ACM Great Lakes Symposium on VLSI, page 149-152. ACM, (2001)A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction., , , , and . ICCD, page 574-584. IEEE Computer Society, (2005)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)Designing for a gigahertz guTS integer processor., , , , , , , and . IEEE Micro, 18 (3): 66-74 (1998)A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology., , , , , , and . ISSCC, page 312-313. IEEE, (2007)Circuit design techniques for a gigahertz integer microprocessor., and . ICCD, page 11-16. (1998)