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Disambiguation of "Nowka, Kevin J."

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Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.

, , , and . IEEE Trans. VLSI Syst., 15 (11): 1215-1224 (2007)

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Kevin Gutsche University of Stuttgart

J. K\"astner

J. Schwarz

J. K\"astner

J Walter

 

Other publications of authors with the same name

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating., , , and . IEEE Trans. VLSI Syst., 15 (11): 1215-1224 (2007)Characterization and design for variability and reliability., , and . CICC, page 341-346. IEEE, (2008)A Scheme for On-Chip Timing Characterization., , , and . VTS, page 24-29. IEEE Computer Society, (2006)On-Chip Delay Measurement Based Response Analysis for Timing Characterization., , , , , and . J. Electronic Testing, 26 (6): 599-619 (2010)A fast hybrid carry-lookahead/carry-select adder design., , and . ACM Great Lakes Symposium on VLSI, page 149-152. ACM, (2001)A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction., , , , and . ICCD, page 574-584. IEEE Computer Society, (2005)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)Designing for a gigahertz guTS integer processor., , , , , , , and . IEEE Micro, 18 (3): 66-74 (1998)The design and application of the PowerPC 405LP energy-efficient system-on-a-chip., , and . IBM Journal of Research and Development, 47 (5-6): 631-640 (2003)A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology., , , , , , and . ISSCC, page 312-313. IEEE, (2007)