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Disambiguation of "Carpenter, Gary D."

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On-Chip Delay Measurement Based Response Analysis for Timing Characterization.

, , , , , and . J. Electronic Testing, 26 (6): 599-619 (2010)

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Vincent Carpenter University of Stuttgart

D. Marino

D. Roth

D. Inkermann

D. Roth

 

Other publications of authors with the same name

Experience with building a commodity Intel-based ccNUMA system., , , , , , , , , and 5 other author(s). IBM Journal of Research and Development, 45 (2): 207-228 (2001)The design and application of the PowerPC 405LP energy-efficient system-on-a-chip., , and . IBM Journal of Research and Development, 47 (5-6): 631-640 (2003)A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor., , , , , , , , and . ISSCC, page 398-399. IEEE, (2007)A Scheme for On-Chip Timing Characterization., , , and . VTS, page 24-29. IEEE Computer Society, (2006)Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs., , and . ICCD, page 134-139. IEEE Computer Society, (2003)On-Chip Delay Measurement Based Response Analysis for Timing Characterization., , , , , and . J. Electronic Testing, 26 (6): 599-619 (2010)Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor., , , , , , , , and . ISLPED, page 193-198. IEEE, (2013)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)