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Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor., , , , , , , , and . ISLPED, page 193-198. IEEE, (2013)CGaAs PowerPC FXU., , , , , , , and . DAC, page 730-735. ACM, (2000)Introducing the Adaptive Energy Management Features of the Power7 Chip., , , , , , , , , and 1 other author(s). IEEE Micro, 31 (2): 60-75 (2011)A microprocessor design project in an introductory VLSI course., , , and . IEEE Trans. Education, 43 (3): 353-361 (2000)Voltage droop reduction using throttling controlled by timing margin feedback., , , , , and . VLSIC, page 96-97. IEEE, (2012)A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor., , , , , , , , and . ISSCC, page 398-399. IEEE, (2007)Runtime power reduction capability of the IBM POWER7+ chip., , , , , , , , , and . IBM Journal of Research and Development, (2013)Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths., , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (11): 2714-2718 (2015)Active Guardband Management in Power7+ to Save Energy and Maintain Reliability., , , , , , , and . IEEE Micro, 33 (4): 35-45 (2013)Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI., , and . VLSI-SOC, page 263-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)