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A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.

F. Gebara, J. Schaub, T. Nguyen, J. Pena, I. Vo, D. Boerstler, and K. Nowka. ISSCC, page 312-313. IEEE, (2007)

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Dr. Marie Davidova University of Stuttgart

David Skuddis University of Stuttgart

DMSA : Dense Multi Scan Adjustment for LiDAR Inertial Odometry and Global OptimizationD. Skuddis, and N. Haala. 2024 IEEE International Conference on Robotics and Automation (ICRA), page 12027-12033. IEEE, (2024)

Other publications of authors with the same name

A new test and characterization scheme for 10+ GHz low jitter wide band PLL.K. Miki, D. Boerstler, E. Hailu, J. Qi, S. Pettengill, and Y. Goto. ASP-DAC, page 856-859. IEEE, (2006)A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.F. Gebara, J. Schaub, T. Nguyen, J. Pena, I. Vo, D. Boerstler, and K. Nowka. ISSCC, page 312-313. IEEE, (2007)Implementation of the 65nm Cell Broadband Engine.M. Riley, B. Flachs, S. Dhong, G. Gervais, S. Weitzel, M. Wang, D. Boerstler, M. Bolliger, J. Keaty, J. Pille and 4 other author(s). CICC, page 717-720. IEEE, (2007)Design methodology for a 1.0 GHz microprocessor.S. Posluszny, N. Aoki, D. Boerstler, J. Burns, S. Dhong, U. Ghoshal, H. Hofstee, D. LaPotin, K. Lee, D. Meltzer and 5 other author(s). ICCD, page 17-23. (1998)"Timing closure by design, " a high frequency microprocessor design methodology.S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong, B. Flachs, H. Hofstee, N. Kojima, O. Kwon, K. Lee and 7 other author(s). DAC, page 712-717. ACM, (2000)IBM Enterprise Systems multimode fiber optic technology.N. Aulet, D. Boerstler, G. DeMario, F. Ferraiolo, C. Hayward, C. Heath, A. Huffman, W. Kelly, G. Peterson, and D. Jr.. IBM Journal of Research and Development, 36 (4): 553-576 (1992)On-chip circuit for measuring multi-GHz clock signal waveforms.K. Jenkins, P. Restle, P. Wang, D. Hogenmiller, D. Boerstler, and T. Bucelot. VTS, page 1-4. IEEE Computer Society, (2013)True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.J. Liberty, A. Barrera, D. Boerstler, T. Chadwick, S. Cottier, H. Hofstee, J. Rosser, and M. Tsai. IBM Journal of Research and Development, (2013)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.E. Fluhr, S. Baumgartner, D. Boerstler, J. Bulzacchelli, T. Diemoz, D. Dreps, G. English, J. Friedrich, A. Gattiker, T. Gloekler and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)

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Disambiguation of "Boerstler, David"

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A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.

Please choose a person to relate this publication to

Dr. Marie Davidova University of Stuttgart

David Stieler University of Stuttgart

Dr. David Boehringer University of Stuttgart

David Werner University of Stuttgart

David Skuddis University of Stuttgart

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Disambiguation

PUMA

Disambiguation of "Boerstler, David"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.

Please choose a person to relate this publication to

Dr. Marie Davidova University of Stuttgart

David Stieler University of Stuttgart

Dr. David Boehringer University of Stuttgart

David Werner University of Stuttgart

David Skuddis University of Stuttgart

Other publications of authors with the same name

Disambiguation

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A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.