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Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.

, , , , and . ISQED, page 88-93. IEEE Computer Society, (2005)

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Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization., , , , and . ISQED, page 88-93. IEEE Computer Society, (2005)Power Gating with Multiple Sleep Modes., , , and . ISQED, page 633-637. IEEE Computer Society, (2006)Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices., , and . ISQED, page 158-162. IEEE, (2010)High performance level conversion for dual VDD design., and . IEEE Trans. VLSI Syst., 12 (9): 926-936 (2004)Improved a priori interconnect predictions and technology extrapolation in the GTX system., , , , , , , and . IEEE Trans. VLSI Syst., 11 (1): 3-14 (2003)Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference., , , , and . J. Solid-State Circuits, 52 (1): 3-7 (2017)A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory., , , and . J. Solid-State Circuits, 51 (4): 1009-1021 (2016)SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS., , , , and . J. Solid-State Circuits, 50 (5): 1310-1323 (2015)A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS., , , , and . J. Solid-State Circuits, 47 (1): 23-34 (2012)A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering., , , , and . J. Solid-State Circuits, 51 (4): 919-929 (2016)