PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Ali, Tamer"

Author of the publication

copydeleteadd this publication to your clipboard
A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

, , , , , , , , , , and . CICC, page 1-4. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ali Salehi University of Stuttgart

Layal Ali University of Stuttgart

Dr. -Ing. Ali Jamshed University of Stuttgart

Ali Hangi University of Stuttgart

Ali Nakhaee University of Stuttgart

 

Other publications of authors with the same name

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 47 (12): 3249-3260 (2012)A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). VLSIC, page 348-. IEEE, (2015)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2013)A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology., , , , , , , , , and 9 other author(s). ISSCC, page 118-120. IEEE, (2019)A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission., , , , , , , , , and 5 other author(s). ISSCC, page 330-332. IEEE, (2012)A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding., , , , , and . VLSIC, page 108-109. IEEE, (2012)Simulation of electronics manufacturing and assembly operations: a survey., , and . Winter Simulation Conference, page 773-779. ACM Press, (1993)A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 51 (4): 881-892 (2016)29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 484-485. IEEE, (2017)A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding., , , and . J. Solid-State Circuits, 48 (4): 1085-1098 (2013)