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Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links., , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2096-2107 (2011)Power Optimized ADC-Based Serial Link Receiver., , and . J. Solid-State Circuits, 47 (4): 938-951 (2012)ADC-Based Serial I/O Receivers., and . IEEE Trans. on Circuits and Systems, 57-I (9): 2248-2258 (2010)Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric., , , , , , , , , and . J. Solid-State Circuits, 43 (9): 2144-2156 (2008)A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm., , , , , , and . J. Solid-State Circuits, 48 (11): 2693-2704 (2013)A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS., , , and . ISCAS, page 2443-2447. IEEE, (2013)ADC-based serial I/O receivers., and . CICC, page 323-330. IEEE, (2009)A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology., , , , , , , , , and 9 other author(s). ISSCC, page 118-120. IEEE, (2019)A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding., , , , , and . VLSIC, page 108-109. IEEE, (2012)A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)