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Disambiguation of "Ho, Ron"

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A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding.

, , , , , and . VLSIC, page 108-109. IEEE, (2012)

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Gili Ron University of Stuttgart

Ron Schlesinger University of Stuttgart

Hélène Rondeau University of Stuttgart

Cheng-I Ho University of Stuttgart

Maximilian Hörl University of Stuttgart

Rigorous derivation of discrete fracture models for Darcy flow in the limit of vanishing aperture, and . Networks and heterogeneous media, 19 (1): 114-156 (2024)
 

Other publications of authors with the same name

Research Challenges for On-Chip Interconnection Networks., , , , , and . IEEE Micro, 27 (5): 96-108 (2007)Long Wires and Asynchronous Control., , and . ASYNC, page 240-249. IEEE Computer Society, (2004)Guest Editorial for Special Issue on High-Performance Multichip Interconnections., , and . IEEE Trans. on Circuits and Systems, 57-II (5): 317-318 (2010)A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding., , , , , and . VLSIC, page 108-109. IEEE, (2012)Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication., , , , , , , , , and 2 other author(s). Hot Interconnects, page 13-22. IEEE Computer Society, (2005)Efficient techniques for canceling transceiver noise., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Modeling and Design of High-Radix On-Chip Crossbar Switches., , , and . NOCS, page 20:1-20:8. ACM, (2015)3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration., , , , , , , , , and 8 other author(s). ISSCC, page 54-55. IEEE, (2017)High-performance ULSI: the real limiter to interconnect scaling.. SLIP, page 3. ACM, (2005)10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 47 (9): 2049-2067 (2012)