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Disambiguation of "Ahmadi, Mahmoud Reza"

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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

, , , , , , , , , , and . CICC, page 1-4. IEEE, (2013)

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Mahmoud Ashour University of Stuttgart

Hamid Reza Madadi Varzaneh University of Stuttgart

 

Other publications of authors with the same name

A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links., , and . CICC, page 125-128. IEEE, (2009)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2013)A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 105-108. IEEE, (2014)High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator., , , and . ISCAS, page 3896-3899. IEEE, (2007)Constrained Partial Response Receivers for High-Speed Links., , and . IEEE Trans. on Circuits and Systems, 55-II (10): 1006-1010 (2008)A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links., , , , , , , , and . J. Solid-State Circuits, 50 (2): 426-439 (2015)A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS., , , , , , , , and . ISSCC, page 34-35. IEEE, (2013)FEXT Crosstalk Cancellation for High-Speed Serial Link Design., , , and . CICC, page 405-408. IEEE, (2006)A 3, times, 5-Gb/s Multilane Low-Power 0.18-muhbox m CMOS Pseudorandom Bit Sequence Generator., , , and . IEEE Trans. on Circuits and Systems, 55-II (5): 432-436 (2008)A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links., , and . J. Solid-State Circuits, 45 (8): 1533-1541 (2010)