Author of the publication

s Serial Links.

B. Zhang, A. Nazemi, A. Garg, N. Kocaman, M. Ahmadi, M. Khanpour, H. Zhang, J. Cao, and A. Momtaz. J. Solid-State Circuits, 50 (2): 426-439 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Momtaz, Afshin

add a person with the name Momtaz, Afshin

Other publications of authors with the same name

An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition.N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, A. Nazemi, U. Singh, and A. Momtaz. J. Solid-State Circuits, 48 (8): 1875-1884 (2013)A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.B. Raghavan, D. Cui, U. Singh, H. Maarefi, D. Pi, A. Vasani, Z. Huang, A. Momtaz, and J. Cao. ISSCC, page 32-33. IEEE, (2013)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz and 1 other author(s). CICC, page 1-4. IEEE, (2013)A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.U. Singh, A. Garg, B. Raghavan, N. Huang, H. Zhang, Z. Huang, A. Momtaz, and J. Cao. J. Solid-State Circuits, 49 (12): 3116-3129 (2014)A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS.S. Lee, D. Tran, T. Ali, B. Çatli, H. Zhang, W. Zhang, M. Abdul-Latif, Z. Huang, G. Li, M. Ahmadi and 1 other author(s). A-SSCC, page 105-108. IEEE, (2014)A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.D. Cui, B. Raghavan, U. Singh, A. Vasani, Z. Huang, D. Pi, M. Khanpour, A. Nazemi, H. Maarefi, T. Ali and 5 other author(s). ISSCC, page 330-332. IEEE, (2012)An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS.A. Momtaz, and M. Green. ISSCC, page 364-365. IEEE, (2009)A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.N. Kocaman, T. Ali, L. Rao, U. Singh, M. Abdul-Latif, Y. Liu, A. Hafez, H. Park, A. Vasani, Z. Huang and 3 other author(s). J. Solid-State Circuits, 51 (4): 881-892 (2016)A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber.J. Cao, B. Zhang, U. Singh, D. Cui, A. Vasani, A. Garg, W. Zhang, N. Kocaman, D. Pi, B. Raghavan and 3 other author(s). J. Solid-State Circuits, 45 (6): 1172-1185 (2010)11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications.N. Kocaman, A. Garg, B. Raghavan, D. Cui, A. Vasani, K. Tang, D. Pi, H. Tong, S. Fallahi, W. Zhang and 4 other author(s). J. Solid-State Circuits, 46 (12): 3089-3100 (2011)

PUMA

Disambiguation of "Momtaz, Afshin"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Momtaz, Afshin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.