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B. Zhang, A. Nazemi, A. Garg, N. Kocaman, M. Ahmadi, M. Khanpour, H. Zhang, J. Cao, and A. Momtaz. J. Solid-State Circuits, 50 (2): 426-439 (2015)

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An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition.N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, A. Nazemi, U. Singh, and A. Momtaz. J. Solid-State Circuits, 48 (8): 1875-1884 (2013)A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS.S. Lee, D. Tran, T. Ali, B. Çatli, H. Zhang, W. Zhang, M. Abdul-Latif, Z. Huang, G. Li, M. Ahmadi and 1 other author(s). A-SSCC, page 105-108. IEEE, (2014)A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.B. Raghavan, D. Cui, U. Singh, H. Maarefi, D. Pi, A. Vasani, Z. Huang, A. Momtaz, and J. Cao. ISSCC, page 32-33. IEEE, (2013)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz and 1 other author(s). CICC, page 1-4. IEEE, (2013)A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.U. Singh, A. Garg, B. Raghavan, N. Huang, H. Zhang, Z. Huang, A. Momtaz, and J. Cao. J. Solid-State Circuits, 49 (12): 3116-3129 (2014)A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.D. Cui, B. Raghavan, U. Singh, A. Vasani, Z. Huang, D. Pi, M. Khanpour, A. Nazemi, H. Maarefi, T. Ali and 5 other author(s). ISSCC, page 330-332. IEEE, (2012)An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS.A. Momtaz, and M. Green. J. Solid-State Circuits, 45 (3): 629-639 (2010)A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS.B. Raghavan, D. Cui, U. Singh, H. Maarefi, D. Pi, A. Vasani, Z. Huang, B. Çatli, A. Momtaz, and J. Cao. J. Solid-State Circuits, 48 (12): 3219-3228 (2013)A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.A. Garg, U. Singh, N. Huang, W. Wong, B. Liu, Z. Huang, A. Momtaz, and J. Cao. VLSIC, page 1-2. IEEE, (2014)A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.B. Zhang, A. Nazemi, A. Garg, N. Kocaman, M. Ahmadi, M. Khanpour, H. Zhang, J. Cao, and A. Momtaz. J. Solid-State Circuits, 50 (2): 426-439 (2015)

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A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.

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Disambiguation of "Momtaz, Afshin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.

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A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.