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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman. CICC, page 1-4. IEEE, (2013)

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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz and 1 other author(s). CICC, page 1-4. IEEE, (2013)3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS.B. Zhang, K. Khanoyan, H. Hatamkhani, H. Tong, K. Hu, S. Fallahi, K. Vakilian, and A. Brewster. ISSCC, page 1-3. IEEE, (2015)An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition.N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, A. Nazemi, U. Singh, and A. Momtaz. J. Solid-State Circuits, 48 (8): 1875-1884 (2013)11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications.N. Kocaman, A. Garg, B. Raghavan, D. Cui, A. Vasani, K. Tang, D. Pi, H. Tong, S. Fallahi, W. Zhang and 4 other author(s). J. Solid-State Circuits, 46 (12): 3089-3100 (2011)11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications.N. Kocaman, A. Garg, B. Raghavan, D. Cui, A. Vasani, K. Tang, D. Pi, H. Tong, S. Fallahi, W. Zhang and 4 other author(s). ISSCC, page 142-144. IEEE, (2011)A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS.B. Zhang, K. Khanoyan, H. Hatamkhani, H. Tong, K. Hu, S. Fallahi, M. Abdul-Latif, K. Vakilian, I. Fujimori, and A. Brewster. J. Solid-State Circuits, 50 (12): 3089-3100 (2015)An 8.5-11.5Gbps SONET transceiver with referenceless frequency acquisition.N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, and A. Momtaz. CICC, page 1-4. IEEE, (2012)A 19 mW/lane Serdes transceiver for SFI-5.1 application.S. Fallahi, D. Cui, D. Pi, R. Zhu, G. Unruh, M. Lugthart, and A. Momtaz. CICC, page 1-4. IEEE, (2011)

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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.