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A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS.

, , , , , , , , , and . J. Solid-State Circuits, 50 (12): 3089-3100 (2015)

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3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS., , , , , , , and . ISSCC, page 1-3. IEEE, (2015)3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A CMOS 434/868 MHz FSK/OOK transmitter with integrated fractional-N PLL., , , , and . APCCAS, page 546-549. IEEE, (2008)Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS., , , and . CICC, page 1-4. IEEE, (2011)0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking., , , , , , and . J. Solid-State Circuits, 47 (8): 1842-1853 (2012)A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS., , , , and . J. Solid-State Circuits, 45 (4): 899-908 (2010)29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 484-485. IEEE, (2017)A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis., , and . IEEE Trans. VLSI Syst., 20 (7): 1336-1341 (2012)A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization., , , , , and . J. Solid-State Circuits, 46 (5): 1076-1088 (2011)A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing., , and . VLSI-DAT, page 1-4. IEEE, (2012)