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Disambiguation of "Çatli, Burak"

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3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS.

, , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Burak Güven Özat University of Stuttgart

 

Other publications of authors with the same name

A 60 GHz CMOS combined mm-wave VCO/divider with 10-GHz tuning range., and . CICC, page 665-668. IEEE, (2009)Triple-Push Operation for Combined Oscillation/Divison Functionality in Millimeter-Wave Frequency Synthesizers., and . J. Solid-State Circuits, 45 (8): 1575-1589 (2010)3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS., , , , , , , , and . ISSCC, page 58-59. IEEE, (2016)29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 484-485. IEEE, (2017)A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications., and . ISCAS, page 996-999. IEEE, (2008)A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS., , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3219-3228 (2013)3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2013)A 30-GHz Triple-push Oscillator on Silicon for mm-wave Applications., and . ISCAS, page 2037-2040. IEEE, (2009)A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 105-108. IEEE, (2014)