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Disambiguation of "Chiang, Patrick Yin"

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0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.

, , , , , , and . J. Solid-State Circuits, 47 (8): 1842-1853 (2012)

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Patrick Gralka University of Stuttgart

Patrick Maisenhölder University of Stuttgart

Patrick Lerge University of Stuttgart

Patrick Hippold University of Stuttgart

Patrick Mesmer University of Stuttgart

 

Other publications of authors with the same name

All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS., and . CICC, page 1-4. IEEE, (2011)A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS., , , , , and . CICC, page 1-4. IEEE, (2013)A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces., , , , and . CICC, page 1-4. IEEE, (2014)A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system., , , , and . ASICON, page 1-4. IEEE, (2015)22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 1-3. IEEE, (2015)Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier for High-Speed High-Sensitivity Optical Communication., , , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (10): 3676-3689 (2019)A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects., , and . IEEE Trans. VLSI Syst., 24 (2): 578-586 (2016)A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS., , , , , and . J. Solid-State Circuits, 48 (5): 1276-1289 (2013)Innovative approach to server performance and power monitoring in data centers using wireless sensors (invited paper)., , , , and . RWS, page 99-102. IEEE, (2012)A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS., , , , , and . J. Solid-State Circuits, 47 (10): 2444-2453 (2012)