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A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.

, , , , , , , , , , , , and . J. Solid-State Circuits, 51 (4): 881-892 (2016)

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A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 105-108. IEEE, (2014)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2013)Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators., and . J. Solid-State Circuits, 47 (6): 1278-1294 (2012)A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). VLSIC, page 348-. IEEE, (2015)A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS., , , , , , , , , and . J. Solid-State Circuits, 50 (12): 3089-3100 (2015)A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 51 (4): 881-892 (2016)A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS., , and . J. Solid-State Circuits, 48 (9): 2104-2117 (2013)A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable N -Push Frequency Multiplication., , and . J. Solid-State Circuits, 46 (6): 1265-1283 (2011)