PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Vasani, Anand"

Author of the publication

copydeleteadd this publication to your clipboard
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.

, , , , , , , , , , , , , , and . J. Solid-State Circuits, 47 (12): 3249-3260 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Anand Venkatachalam University of Stuttgart

Mahathi Anand University of Stuttgart

 

Other publications of authors with the same name

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 47 (12): 3249-3260 (2012)A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). VLSIC, page 348-. IEEE, (2015)A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS., , , , , , , , and . ISSCC, page 32-33. IEEE, (2013)A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission., , , , , , , , , and 5 other author(s). ISSCC, page 330-332. IEEE, (2012)A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS., , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3219-3228 (2013)21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber., , , , , , , , , and 3 other author(s). ISSCC, page 370-371. IEEE, (2009)A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 51 (4): 881-892 (2016)A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 45 (6): 1172-1185 (2010)11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 46 (12): 3089-3100 (2011)11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications., , , , , , , , , and 4 other author(s). ISSCC, page 142-144. IEEE, (2011)