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Disambiguation of "Meghelli, Mounir"

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A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

, , , , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 49 (11): 2474-2489 (2014)

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Other publications of authors with the same name

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08)., and . J. Solid-State Circuits, 43 (10): 2175-2176 (2008)A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 47 (8): 1828-1841 (2012)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (12): 3458-3473 (2017)A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2011)A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 49 (11): 2474-2489 (2014)Errata Erratum to Ä 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . J. Solid-State Circuits, 55 (4): 1124 (2020)Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits., , , and . Proc. IEEE, 88 (10): 1572-1582 (2000)A linearized voltage-controlled oscillator for dual-path phase-locked loops., , and . ISCAS, page 2678-2681. IEEE, (2013)