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Disambiguation of "Francese, Pier Andrea"

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A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

, , , , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 49 (11): 2474-2489 (2014)

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Dr. Andrea Thom University of Stuttgart

Andrea Loi University of Stuttgart

Andrea Talmann University of Stuttgart

Jun. -Prof. Dr. Andrea Iannelli University of Stuttgart

Dr. Andrea Zappe University of Stuttgart

 

Other publications of authors with the same name

20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (3): 636-648 (2016)5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory., , , , , and . CoRR, (2019)A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS., , , , , , , , , and . VLSI Circuits, page 53-54. IEEE, (2018)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 55 (1): 38-48 (2020)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS., , , , , , , , and . ISSCC, page 408-409. IEEE, (2013)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)