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A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

G. Gangasani, C. Hsu, J. Bulzacchelli, T. Beukema, W. Kelly, H. Xu, D. Freitas, A. Prati, D. Gardellini, R. Reutemann, G. Cervelli, J. Hertle, M. Baecher, J. Garlett, P. Francese, J. Ewen, D. Hanson, D. Storaska, and M. Meghelli. J. Solid-State Circuits, 49 (11): 2474-2489 (2014)

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John Nixon University of Stuttgart

F. Dörr

Isaac Henderson Johnson Jeyakumar University of Stuttgart

F. Laufer

F. Rusitschka

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CMOS circuits for Gb/s serial data communication.J. Ewen, M. Soyuer, A. Widmer, K. Wrenner, B. Parker, and H. Ainspan. IBM Journal of Research and Development, 39 (1-2): 73-82 (1995)Opportunities for Standard Silicon Technology in RF&Microwave ApplicationsJ. Burghartz, M. Soyuer, K. Jenkins, Y. Kwark, S. Ponnapalli, J. Ewen, and W. Pence. ESSDERC '95 : proceedings of the 25th European Solid State Device Research Conference, The Netherlands Congress Centre, The Hague, The Netherlands, 25th - 27th September 1995, page 363-367. Gif-sur-Yvette, Éditions Frontières, (1995)Multilevel Monolithic Inductors in Silicon TechnologyM. Soyuer, J. Burghartz, K. Jenkins, S. Ponnapalli, J. Ewen, and W. Pence. Electronics Letters, 31 (5): 359-360 (March 1995)A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.G. Gangasani, C. Hsu, J. Bulzacchelli, T. Beukema, W. Kelly, H. Xu, D. Freitas, A. Prati, D. Gardellini, R. Reutemann and 9 other author(s). J. Solid-State Circuits, 49 (11): 2474-2489 (2014)A 2.4-GHz Silicon Bipolar Oscillator with Integrated ResonatorM. Soyuer, K. Jenkins, J. Burghartz, H. Ainspan, F. Canora, S. Ponnapalli, J. Ewen, and W. Pence. IEEE Journal of Solid-State Circuits, 31 (2): 268-270 (February 1996)A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery.M. Soyuer, H. Ainspan, and J. Ewen. ISCAS, page 187-190. IEEE, (1995)

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Disambiguation of "Ewen, John F."

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A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

Please choose a person to relate this publication to

John Nixon University of Stuttgart

F. Dörr

Isaac Henderson Johnson Jeyakumar University of Stuttgart

F. Laufer

F. Rusitschka

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Ewen, John F."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

Please choose a person to relate this publication to

John Nixon University of Stuttgart

F. Dörr

Isaac Henderson Johnson Jeyakumar University of Stuttgart

F. Laufer

F. Rusitschka

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.