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Disambiguation of "Andersen, Toke Meyer"

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20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS.

, , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Matthias Meyer University of Stuttgart

Hon. -Prof. Dr. Ole Andersen University of Stuttgart

Florian Meyer University of Stuttgart

Jens Meyer University of Stuttgart

Bernd Meyerer University of Stuttgart

 

Other publications of authors with the same name

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS., , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3049-3058 (2013)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (3): 636-648 (2016)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS., , , , , , , , and . ISSCC, page 408-409. IEEE, (2013)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS., , , , , , , , and . J. Solid-State Circuits, 48 (12): 3268-3284 (2013)A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS., , , , , , , , , and 2 other author(s). ESSCIRC, page 148-151. IEEE, (2015)A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 89-92. IEEE, (2014)