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A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS., , , , , , , and . ISSCC, page 226-598. IEEE, (2007)A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 89-92. IEEE, (2014)A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI., , , , , , and . ISSCC, page 446-614. IEEE, (2007)BiCMOS Variable Gain LNA at C-Band with Ultra Low Power Consumption for WLAN., , , , , , and . ICT, volume 3124 of Lecture Notes in Computer Science, page 891-899. Springer, (2004)A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS., , , , , , and . ISSCC, page 160-161. IEEE, (2010)A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS., , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3049-3058 (2013)Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components., , and . IEEE Trans. Communications, 54 (9): 1554-1557 (2006)Jitter Measurements of High-Speed Serial Links., and . IEEE Design & Test of Computers, 21 (6): 536-543 (2004)A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS., , , , , , and . J. Solid-State Circuits, 45 (12): 2850-2860 (2010)A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS., , , , , , , , and . ISSCC, page 110-111. IEEE, (2008)