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Disambiguation of "Karnik, Tanay"

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Adaptive and Resilient Circuits for Dynamic Variation Tolerance.

, , , , and . IEEE Design & Test, 30 (6): 8-17 (2013)

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Other publications of authors with the same name

Accurate Estimation of SRAM Dynamic Stability., , , , , and . IEEE Trans. VLSI Syst., 16 (12): 1639-1647 (2008)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters., , , , , , and . J. Solid-State Circuits, 42 (1): 66-73 (2007)Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies., , and . VLSI Design, page 5-7. IEEE Computer Society, (2006)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors., , , , , , , and . DAC, page 486-491. ACM, (2002)An empirical model for accurate estimation of routing delay in FPGAs., and . ICCAD, page 328-331. IEEE Computer Society / ACM, (1995)Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power., , , and . IEEE Trans. VLSI Syst., 16 (12): 1609-1619 (2008)A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance., , , , and . J. Solid-State Circuits, 48 (4): 907-916 (2013)Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference., , , , and . J. Solid-State Circuits, 47 (1): 3-7 (2012)