PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Karnik, Tanay"

Author of the publication

copydeleteadd this publication to your clipboard
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.

, , , and . IEEE Trans. VLSI Syst., 16 (12): 1609-1619 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Karnik, Tanay
add a person with the name Karnik, Tanay
 

Other publications of authors with the same name

Accurate Estimation of SRAM Dynamic Stability., , , , , and . IEEE Trans. VLSI Syst., 16 (12): 1639-1647 (2008)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters., , , , , , and . J. Solid-State Circuits, 42 (1): 66-73 (2007)Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors., , , , , , , and . DAC, page 486-491. ACM, (2002)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)An empirical model for accurate estimation of routing delay in FPGAs., and . ICCAD, page 328-331. IEEE Computer Society / ACM, (1995)Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies., , and . VLSI Design, page 5-7. IEEE Computer Society, (2006)Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration., , and . IET Computers & Digital Techniques, 5 (3): 205-212 (2011)Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes., , and . IEEE Trans. Dependable Sec. Comput., 1 (2): 128-143 (2004)A 22nm dynamically adaptive clock distribution for voltage droop tolerance., , , , and . VLSIC, page 94-95. IEEE, (2012)