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A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.

K. Bowman, C. Tokunaga, T. Karnik, V. De, and J. Tschanz. J. Solid-State Circuits, 48 (4): 907-916 (2013)

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Accurate Estimation of SRAM Dynamic Stability.D. Khalil, M. Khellah, N. Kim, Y. Ismail, T. Karnik, and V. De. IEEE Trans. VLSI Syst., 16 (12): 1639-1647 (2008)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.D. Somasekhar, Y. Ye, P. Aseron, S. Lu, M. Khellah, J. Howard, G. Ruhl, T. Karnik, S. Borkar, V. De and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters.P. Hazucha, S. Moon, G. Schrom, F. Paillet, D. Gardner, S. Rajapandian, and T. Karnik. J. Solid-State Circuits, 42 (1): 66-73 (2007)Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.R. Puri, T. Karnik, and R. Joshi. VLSI Design, page 5-7. IEEE Computer Society, (2006)Circuit techniques for dynamic variation tolerance.K. Bowman, J. Tschanz, C. Wilkerson, S. Lu, T. Karnik, V. De, and S. Borkar. DAC, page 4-7. ACM, (2009)Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.T. Karnik, Y. Ye, J. Tschanz, L. Wei, S. Burns, V. Govindarajulu, V. De, and S. Borkar. DAC, page 486-491. ACM, (2002)An empirical model for accurate estimation of routing delay in FPGAs.T. Karnik, and S. Kang. ICCAD, page 328-331. IEEE Computer Society / ACM, (1995)Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes.T. Karnik, P. Hazucha, and J. Patel. IEEE Trans. Dependable Sec. Comput., 1 (2): 128-143 (2004)A 22nm dynamically adaptive clock distribution for voltage droop tolerance.K. Bowman, C. Tokunaga, T. Karnik, V. De, and J. Tschanz. VLSIC, page 94-95. IEEE, (2012)High-frequency DC-DC conversion : fact or fiction.T. Karnik, P. Hazucha, G. Schrom, F. Paillet, and D. Gardner. ISCAS, IEEE, (2006)

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A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.

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A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.