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Demonstration of a Time-predictable Flight Controller on a Multicore Processor., , , , , , and . ISORC, page 95-96. IEEE, (2019)A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip., , , and . Journal of Systems Architecture - Embedded Systems Design, (2017)ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology., and . NOCS, page 55-64. IEEE Computer Society, (2008)Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip., , and . CODES+ISSS, page 481-490. ACM, (2009)Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip., , , and . DSD, page 319-326. IEEE Computer Society, (2013)Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend., , and . IEEE Trans. VLSI Syst., 17 (2): 248-261 (2009)Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation., , , , , and . IEEE Trans. VLSI Syst., 24 (2): 479-492 (2016)A Time-Predictable Memory Network-on-Chip., , , and . WCET, volume 39 of OASIcs, page 53-62. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)Design of delay insensitive circuits using multi-ring structures., , and . EURO-DAC, page 15-20. IEEE Computer Society Press, (1992)Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools., , , and . NORCHIP, page 1-6. IEEE, (2014)