PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Kajihara, Seiji"

Author of the publication

copydeleteadd this publication to your clipboard
Analysis and mitigation or IR-Drop induced scan shift-errors

, , , , , , , and . 2017 IEEE International Test Conference (ITC), Piscataway, IEEE, (2017)
DOI: 10.1109/TEST.2017.8242055

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Kajihara, Seiji
add a person with the name Kajihara, Seiji
 

Other publications of authors with the same name

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling., , , , , , , , , and 1 other author(s). Asian Test Symposium, page 90-95. IEEE Computer Society, (2011)On Test Data Volume Reduction for Multiple Scan Chain Designs., , , and . VTS, page 103-110. IEEE Computer Society, (2002)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , and . ATS, page 203-208. IEEE Computer Society, (2016)A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths., , , and . VLSI Design, page 82-87. IEEE Computer Society, (1997)Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing., , , , , , and . J. Electronic Testing, 24 (4): 379-391 (2008)Stuck-open faults test generation for cmos combinational circuits., , and . Systems and Computers in Japan, 22 (9): 33-42 (1991)Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement., , and . IEICE Transactions, 78-D (7): 861-867 (1995)A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits., , , , and . IEICE Transactions, 91-D (3): 667-674 (2008)Synthesis for Testability by Sequential Redundancy Removal Using Retiming., , and . FTCS, page 33-40. IEEE Computer Society, (1995)