PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Miyase, Kohei"

Author of the publication

copydeleteadd this publication to your clipboard
On Test Data Volume Reduction for Multiple Scan Chain Designs.

, , , and . VTS, page 103-110. IEEE Computer Society, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Miyase, Kohei
add a person with the name Miyase, Kohei
 

Other publications of authors with the same name

Don't Care Identification and Statistical Encoding for Test Data Compression., , , , and . IEICE Transactions, 87-D (3): 544-550 (2004)On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression., , , , , and . VLSI Design, page 279-284. IEEE Computer Society, (2013)A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)On Improving Defect Coverage of Stuck-at Fault Tests., , , , and . Asian Test Symposium, page 216-223. IEEE Computer Society, (2005)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , , , and . IEICE Transactions, 97-D (10): 2706-2718 (2014)A Method of Static Test Compaction Based on Don't Care Identification., , and . DELTA, page 392-395. IEEE Computer Society, (2002)LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing., , , , , and . IEEE Design & Test, 30 (4): 60-70 (2013)Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory., , and . IOLTS, page 226-227. IEEE, (2018)Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors, , , , , , , and . Proceedings of the IEEE International Test Conference (ITC'17), page 1--8. Fort Worth, Texas, USA, (2017)A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits., , , , and . IEICE Transactions, 91-D (3): 667-674 (2008)