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Disambiguation of "Yamato, Yuta"

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A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.

, , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)

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Other publications of authors with the same name

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)An ECC-based memory architecture with online self-repair capabilities for reliability enhancement., , , , and . ETS, page 1-6. IEEE, (2015)A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation., , , and . ITC, page 1-8. IEEE Computer Society, (2012)LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing., , , , , and . IEEE Design & Test, 30 (4): 60-70 (2013)Power-aware test generation with guaranteed launch safety for at-speed scan testing., , , , , , , and . VTS, page 166-171. IEEE Computer Society, (2011)A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment., , , , , , , and . ICCAD, page 97-104. ACM, (2009)Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair., , , , and . IEICE Transactions, 99-D (10): 2591-2599 (2016)CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing., , , , , , , and . ATS, page 397-402. IEEE Computer Society, (2008)A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing., , , , , , and . IEICE Transactions, 96-D (9): 2003-2011 (2013)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , and 1 other author(s). IEICE Transactions, 93-A (7): 1309-1318 (2010)