%0 Conference Paper %1 conf/ats/FurukawaWMYKGWT08 %A Furukawa, Hiroshi %A Wen, Xiaoqing %A Miyase, Kohei %A Yamato, Yuta %A Kajihara, Seiji %A Girard, Patrick %A Wang, Laung-Terng %A Tehranipoor, Mark %B ATS %D 2008 %I IEEE Computer Society %K dblp %P 397-402 %T CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. %U http://dblp.uni-trier.de/db/conf/ats/ats2008.html#FurukawaWMYKGWT08 %@ 978-0-7695-3396-4

@inproceedings{conf/ats/FurukawaWMYKGWT08, added-at = {2016-02-01T00:00:00.000+0100}, author = {Furukawa, Hiroshi and Wen, Xiaoqing and Miyase, Kohei and Yamato, Yuta and Kajihara, Seiji and Girard, Patrick and Wang, Laung-Terng and Tehranipoor, Mark}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b6f36437d088cb7508e70f9882bf8bfe/dblp}, booktitle = {ATS}, crossref = {conf/ats/2008}, ee = {http://doi.ieeecomputersociety.org/10.1109/ATS.2008.27}, interhash = {a76d85a86135530662cba2ee4df266fb}, intrahash = {b6f36437d088cb7508e70f9882bf8bfe}, isbn = {978-0-7695-3396-4}, keywords = {dblp}, pages = {397-402}, publisher = {IEEE Computer Society}, timestamp = {2016-09-07T09:33:38.000+0200}, title = {CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.}, url = {http://dblp.uni-trier.de/db/conf/ats/ats2008.html#FurukawaWMYKGWT08}, year = 2008 }