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Disambiguation of "Miyase, Kohei"

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CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

, , , , , , , and . ATS, page 397-402. IEEE Computer Society, (2008)

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Other publications of authors with the same name

On Improving Defect Coverage of Stuck-at Fault Tests., , , , and . Asian Test Symposium, page 216-223. IEEE Computer Society, (2005)A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)A Method of Static Test Compaction Based on Don't Care Identification., , and . DELTA, page 392-395. IEEE Computer Society, (2002)LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing., , , , , and . IEEE Design & Test, 30 (4): 60-70 (2013)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , , , and . IEICE Transactions, 97-D (10): 2706-2718 (2014)Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory., , and . IOLTS, page 226-227. IEEE, (2018)On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression., , , , , and . VLSI Design, page 279-284. IEEE Computer Society, (2013)Don't Care Identification and Statistical Encoding for Test Data Compression., , , , and . IEICE Transactions, 87-D (3): 544-550 (2004)Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors, , , , , , , and . Proceedings of the IEEE International Test Conference (ITC'17), page 1--8. Fort Worth, Texas, USA, (2017)Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling., , , , , , , , , and 1 other author(s). Asian Test Symposium, page 90-95. IEEE Computer Society, (2011)